The complexity of fault detection in MOS VLSI circuits

This paper considers the fault detection problem for a single fault in a single MOS channel-connected subcircuit. We identify the following three decision sub-problems : (i) decide if a test vector exists; (ii) decide if an initializing vector exists; and (iii) decide if a test pair is robust. We prove that each of these problems is NP complete. More importantly, we prove that the rst two remain NP complete for the simplest subcircuit design styles, namely series/parallel nMOS or CMOS logic gates. The third subproblem is shown to be of linear complexity for a CMOS logic gate with a stuck-open fault. We illustrate that a test pair that is not robust may contain a robust sub-test pair, and give a necessary and su cient condition for this to happen in CMOS logic gates. This leads to a linear-time algorithm for CMOS logic gates which tests for robustness and, if possible, derives a robust test pair from a possibly non-robust pair. The implications of these complexity results on practical transistor-level test generation tools are discussed. This work was supported by the Semiconductor Research Corporation under Contract SRC RSCH 84-06-049. y F. N. Najm is now with the Semiconductor Process and Design Center, Texas Instruments Inc., P.O. Box 655621, MS 369, Dallas, Texas 75265